With the continuous improvement of embedded product performance, embedded systems have been rapidly popularized in consumer electronics, automotive, industrial control, communication and other industries. However, due to the high development cost and long R&D cycle of embedded systems, the issues of encrypting key technologies and keeping important data confidential have become increasingly prominent. How to adopt low-cost and high-efficiency methods in these embedded systems to protect research achievements from illegal imitation and plagiarism, while storing some key codes or data, has become one of the problems plaguing many R&D engineers. In addition to legal means to protect intellectual property rights, another simpler and more effective solution is to use encrypted memory chips for hardware circuit encryption and authenticated storage of important data.
The AT88SCxx series of encrypted memory chips are multi-purpose encrypted memory chips produced by Atmel, a world-renowned chip manufacturer, with AT88SC1616 being a typical representative of this series. Equipped with up to 2KB of EEPROM, communicating via the I2C serial bus, and supporting data access through authentication or encryption verification, it is widely used in product development due to its large capacity, small size, ease of use, and high security and reliability.

1 Device Overview

1.1 Pin Description
As shown in Figure 1, in embedded systems, AT88SC1616 is commonly available in two typical packages: SOIC and PDIP. With an I2C serial bus interface, the device features a small number of pins and compact size. The functions of each pin are as follows:

SCL — Serial clock input pin, used to control all data input and output of the device;
SDA — Serial data input/output pin;
VCC — Power supply voltage, operating voltage range: 3.0～5.5V;
GND — Ground;
NC — Not connected.

1.2 Internal Structure

As shown in Figure 2, the internal structure of the AT88SC1616 encrypted memory chip mainly consists of a power management and reset module, a synchronous transmission module, an authentication unit, a password verification unit, a pseudo-random number generator, and an EEPROM. The power management and reset module is mainly responsible for chip power supply, reset management, and power-down protection; the synchronous transmission module controls data transmission under different communication modes; the authentication and password verification units implement security management for data access in the user application area at different security levels; the pseudo-random number generator is used for encryption calculations of the internal encryption engine; the EEPROM stores important encrypted data and codes.
1.3 Main Features
① 256B configuration storage area, which can define chip serial number, passwords, secret keys, authentication seeds, manufacturer information, etc., according to different requirements.
② 2KB user application storage area, which can be divided into 16 independent application partitions according to different security levels, supporting up to 16 users; multiple application partitions with the same security level and password can also be merged.
③ High security. The user application area supports three access modes: standard access, authenticated access, and encrypted verification access, with multiple sets of password sets provided for read and write access. Each application partition has a corresponding register in the configuration area to control its security level and access mode.
④ High reliability. Supports up to 100,000 erase/write cycles and a 10-year data retention period.
⑤ Multiple packages. In addition to 8-pin PDIP and SOIC packages, it also offers smart card packaging, making it widely applicable to IC card systems.
⑥ High speed. The maximum communication rate reaches 1000kb/s via the I2C serial bus.
2 Working Principle
2.1 Configuration Area Structure
The AT88SC1616 logic encryption chip is a serial EEPROM with a 2KB user application storage area and a 256B system configuration area. The application storage area can be configured into 16 application partitions of equal capacity, controlled by 8 sets (16 in total) of read and write passwords, with a maximum error count of 8 times. These 16 application partitions can also be configured to use the same password and security level and merged freely.
The structure of the AT88SC1616 configuration area is shown in Figure 3.

① DCR: Specifies the authentication count limit and chip address.
② AR0～AR7: Determine access permissions, defined during initialization, specifying the access mode of the corresponding user application area (e.g., whether authentication is required, whether a password is used, which password set to use, whether read-only, etc.).
③ AAC: Authentication error counter.
④ PAC: Password error counter.
Each of the 16 user application partitions has two 24-bit passwords, whose read and write operations can be set in the configuration area, and each password has a counter to limit the number of password verification attempts.
2.2 Chip Operation
The AT88SC1616 chip provides three access modes for the user application area: standard, authenticated, and encrypted. This not only allows users to flexibly select encryption modes according to actual conditions but also improves system security. In standard access mode, there are no restrictions on read and write access to the user application area; in authenticated mode, users must pass authentication and the password verification set for different user areas to access the user data area correctly, with data transmitted in plaintext on the bus; in encrypted verification mode, users must first pass authentication, then re-authenticate using the updated data in the specific register of the configuration area as the secret key after successful authentication, and finally pass the password verification set for different user areas to access the user area, with data transmitted in encrypted ciphertext on the bus.
In general, the chip operation can be divided into three steps: initialization, authentication (encryption), and access.
(1) Initialization
During initialization, the MCU of the user system writes manufacturer information, partition settings, security levels, passwords, and parameters required for encryption authentication into the configuration area of the chip, and finally performs a write fuse process. In implementation, focus should be placed on the rational configuration and use of the 256B configuration area of the AT88SC1616 and effective control of access permissions to user partitions, so the configuration of several registers listed in Table 1 is particularly important.
While configuring the configuration area reasonably, three sets of important parameters required for authentication must be written into the corresponding registers of the configuration area. These three sets of parameters are: Ci (Cryptograms) — random number required for authentication, Nc (Identification Number) — chip serial number, and Gc (Secret Seeds) — secret seed derived from the user-defined F1 algorithm.
During initialization, the write password of the configuration area must first be written into the seventh set of password writing areas. Only after correctly writing this password (provided by the chip supplier) can the user obtain the write permission for the entire configuration area. After correctly writing the password, each register of the chip can be configured as required, and finally, the fuse bits must be written with 0 in the order of SEC, PER, CMA, and FAB for fuse processing according to user needs. Note that the information in the configuration area cannot be modified once the chip is fuse-written.
(2) Authentication
The entire authentication process is a two-way authentication process, with the flow shown in Figure 4.
The MCU of the user system first reads Nc and Ci from the chip, calculates Gc according to the user-defined F1(Nc, Ks) algorithm, and simultaneously calculates Q1 using the chip's internal F2(Gc, Ci, Q0) algorithm, then sends the initial authentication parameters Q1 and Q0 (Q0 is a random number generated by the CPU) to the chip. The chip internally calculates Ci+1=F2(Gc, Ci, Q0) using its own F2 logic and obtains Q2=F2(Gc, Q1) at the same time. After receiving the verification and authentication command, the chip judges whether Ci+1=Q1; if yes, Ci+2=F2(Gc, Ci+1) is calculated, Ci is updated with Ci+2, and the authentication inside the chip is passed; at the same time, the value of the SK (Session Encryption Key) in the same group inside the chip is updated. After receiving the updated Ci from the chip, the CPU judges whether it is equal to Q2; if the verification is passed, the entire authentication is successful.

The above process is for the authentication mode. To enter the encrypted verification mode, it is necessary to re-use the updated SK value returned after successful authentication to replace Gc, with Ci as the parameter; the chip and the MCU perform another calculation and comparison using the F2 function, and the encrypted authentication mode is only entered after the values are judged to be equal.
The aforementioned F2 algorithm is a variant of the DES algorithm initialized by the chip's internal control logic using three parameters: Gc, Ci, and Q0. This algorithm is the key to all encryption and decryption, integrity authentication, and information authentication.

(3) Access to User Partitions
After successful authentication (encryption), commands can be sent to select user partitions for data read and write access. If each partition has additional read or write password restrictions, the password must be written into the accessed partition for verification, and only after this step can the user partition be fully accessed. At this time, if multiple user partitions use the same security level and password, these multiple user areas can be merged. It should be noted that the internal encryption engine of the chip starts immediately after successful authentication, and any operation of the MCU on the chip needs to be calculated according to the internal algorithm of the chip's encryption engine to maintain synchronization with it. In particular, after sending a write command and data to the user partition once, the encryption engine result calculated by the MCU must be sent immediately to verify with the result calculated by the chip's internal encryption engine. The chip can only write data to the corresponding address after receiving the correct checksum; otherwise, the data cannot be written to the target address, and the chip will return an error message.
3 Chip Function Implementation

3.1 Hardware Circuit

Since the AT88SC1616 encryption chip adopts the two-wire I2C bus communication mode, the hardware interface with the microprocessor is relatively simple. Figure 5 shows the hardware interface circuit connecting AT88SC1616 with the AVR microcontroller ATmega128. Since ATmega128 has a built-in I2C interface, it can be directly connected to AT88SC1616. In other embedded systems, the interface between AT88SC1616 and other microprocessors is equally simple, requiring only direct connection to the corresponding I2C interface pins. If the system's MCU has no dedicated I2C interface pins, general I/O pins (GPIO) can be used to connect with the clock and data lines of AT88SC1616, and normal operation can be achieved by simulating the I2C protocol. Regardless of whether the I2C protocol is simulated or not, pull-up resistors complying with I2C bus requirements must be provided on the bus to ensure correct timing.
3.2 Software Implementation

AT88SC1616 adopts the two-wire I2C communication mode with relatively simple control timing, which will not be elaborated here. The focus here is on the chip operation process.

The initialization flow of AT88SC1616 is shown in Figure 6. Commands and data are sent to the addresses of each internal register of the chip via the I2C communication mode in the order of writing the configuration area password, partition access mode and read/write passwords, security restrictions and authentication parameters, and fuse processing. Since the AT88SC1616 has an internal memory test area that is not subject to security and password restrictions, read and write tests can be performed on this area first to ensure the correctness of the I2C read/write timing before writing various commands to the chip correctly.
The user area authentication flow is shown in Figure 7. Regardless of whether the system MCU uses its own I2C interface or general I/O pins to simulate I2C, the software implementation follows the aforementioned bus timing. It should be noted that before initiating the I2C START signal, SCL must first send 4 pulses to start communication; otherwise, the sent data and commands will not be correctly received by the chip. This is different from ordinary I2C devices and must be emphasized.
The flow for accessing user partitions is shown in Figure 8. Data can be written to the user partition first and then read back for verification. During programming, it should be noted that after successful authentication, all operations of the MCU on the chip must include calculations for the internal encryption engine. After sending commands and data to the chip, the checksum must be sent immediately to verify with the chip's internal encryption engine; an incorrect checksum will cause the chip to return an error message.
4 Application in Embedded Systems

Due to its many advantages such as ease of use, high security and reliability, AT88SC1616 has broad application prospects in industrial control, consumer electronics, medical devices, billing systems and other fields. The author has applied this chip in the developed selective leakage protection system. In this system, 64 power supply branches are artificially divided into 4 zones, each with independent voltage, current and phase settings. Different user names and passwords are set for administrators of different zones, and these parameters are stored in the user application area of AT88SC1616. To maintain the security of system data, passwords are set for the read and write access of these parameters in the program; incorrect passwords will prevent reading and writing of these parameters, ensuring that only the genuine power supply zone administrators can set the system parameters of the corresponding zones. At the same time, the encrypted verification access mode is adopted, so that the data transmitted on the bus is ciphertext, maintaining the security of system data. To prevent some malicious users from obtaining system timing through illegal means for disassembly to crack the system and seek high profits, two methods are also adopted to ensure the security of the entire system: first, the system performs authenticated access to the chip irregularly, and returns an error message if the system authentication fails once; second, the number of illegal authenticated access attempts is limited, and the chip is locked once the number of errors exceeds 8 times, thus protecting our intellectual property rights.

For security reasons, each chip uses a unique serial number. The author also designed a simple and practical programmer for AT88SC1616 according to actual conditions. Using this programmer, the chip can be initialized before formal use, writing serial number, authentication parameters, security level, access password and other information into the configuration area, so that each initialized chip can be directly applied in other systems, greatly improving efficiency.

Conclusion

This paper introduces in detail the chip structure, features, and data storage and access principles of AT88SC1616, and takes the interface with ATmega128 as an example to present a practical hardware interface circuit and software implementation flow. With its large storage space, strict security performance, and simple, reliable and high-speed data transmission mode, AT88SC1616 greatly improves the data security and applicability of embedded systems. This chip has been successfully applied in the software and hardware encryption system of selective leakage protection. Facts have proved that the use of this chip not only improves the anti-cracking performance of the system but also ensures the security of important data. In addition, a programmer for initializing the chip is designed according to its features, providing hardware conditions for mass production and achieving good results. The excellent security of AT88SC1616 also makes it more widely applicable to embedded systems such as remote meter reading, medical devices, set-top boxes, automobiles, communications, and consumer home appliances. The methods introduced in this paper have good reference value for these applications.

References
1 Atmel. AT88SC1616 DataSheet. 2001
2 Geng Degen. Principle and Application of AVR High-Speed Embedded Microcontrollers. Beijing: Beihang University Press, 2002
3 He Limin. Design of I2C Bus Application Systems. Beijing: Beihang University Press, 1995
Wang Yanwen: Professor, research direction: Power system automation.
Bo Yong: Postgraduate, research direction: Computer control.
Sun Suli: Postgraduate, research direction: Computer application.